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Deep-dive · Brain vs. computer

Inside the Switch: Transistors, Logic, and Bits

What a transistor is, how chips are made, how switches become arithmetic and memory, how a keypress becomes light, how long this has been going on, and how quantum computing differs.

Recap and map

The brain comparison

On the main page's matter-to-thought ladder, the transistor pairs with the ion channel (stage 3, "smallest switch"). Both are gates that open or close depending on voltage, but by different mechanisms: semiconductors and electrons versus proteins and ions. A whole neuron is far more than a gate (stage 5).

You are here: ladder stages 3 and 5 →

D1

The transistor: a switch with no moving parts

Silicon and doping

The MOSFET, the transistor in nearly every chip

Shapes over time: wrapping the gate around the channel

Same switch since 1959; each new shape wraps the gate further around the channel.

  1. 1959MOSFET invented. Its basic structure (gate, channel, source, drain) hasn't changed since.[R2]
  2. 2011FinFET: Intel's 22 nm "Tri-Gate". The gate covers a thin fin on 3 sides.[R3]
  3. Q4 2025Nanosheet (gate-all-around): TSMC N2 in volume production. The gate wraps stacked ribbons on all sides.[R4][R5]
  4. by Oct 2026Intel 18A: RibbonFET plus PowerVia (power from the back). Intel says it's in high-volume production.[R6]
Read the details
  • Planar: the gate sits on top of a flat channel.
  • FinFET (2011): Intel announced its 22 nm "Tri-Gate" transistor on 4 May 2011. The channel becomes a thin vertical fin with the gate on three sides.[R3] Samsung, TSMC and others followed.[R2]
  • Gate-all-around / nanosheet: the fin is replaced by a stack of thin silicon ribbons, and the gate wraps all the way around them for better control.[R4]
    • Samsung said on 30 June 2022 that it had started initial production of its 3 nm process with gate-all-around transistors, which it calls MBCFET.[R97]
    • TSMC's N2 uses its first-generation nanosheet transistors and began volume production in Q4 2025.[R5]
    • Intel's 18A uses "RibbonFET" (gate-all-around) plus "PowerVia", which delivers power from the back of the chip. Intel says 18A is in high-volume production (page read Oct 2026).[R6]
  • Research frontier: Intel has reported a transistor with a 6 nm gate length and a 3 nm-thick nanosheet.[R4]
T1

Transistor cross-section

A transistor is a voltage-controlled switch, and newer shapes just wrap the gate further around the channel.

This demo needs JavaScript.

What this leaves outReal transistors turn on gradually and leak a little when "off". This is a 2D sketch of 3D devices, and no real voltages are shown.

D2

How chips are made

Wafers and steps

1 Deposit add a thin layer 2 Coat light-sensitive resist 3 Lithography print the pattern 4 Etch remove material 5 Implant dope regions ↻ repeated many times at the end 6 Packaging
ASML's six core steps.[R7]
300 mmmost-used wafer size [R7]
thousandsof steps per chip [R7]
3+ monthsdesign to production [R7]
Read the details
  • Chips are built on thin, polished silicon discs called wafers. 300 mm is the size most often used.[R7]
  • ASML (the company that makes the most advanced lithography machines) lists six core steps, repeated many times:[R7]
    1. deposition (add a thin layer)
    2. photoresist coating (add a light-sensitive layer)
    3. lithography (project the pattern with light)
    4. etch (remove material where the pattern says)
    5. ion implantation (dope regions)
    6. packaging
  • Making a chip takes thousands of steps and can take more than three months from design to production.[R7]

Photolithography: printing with light

Printing with light, invented for silicon in 1955.[R8] Shorter light prints finer patterns.

Light wavelength (to scale)

DUV laser248 nm
DUV laser193 nm
EUV, >14× shorter [R9]13.5 nm

Finest detail EUV can print

Standard EUV (NA 0.33)13 nm
High-NA EUV (NA 0.55) [R10]8 nm
Read the details
  • Adapted for silicon at Bell Labs in 1955 (Jules Andrus and Walter Bond), borrowing from photoengraving.[R8]
  • How it works: coat the wafer with a light-sensitive resist, shine light through a patterned mask, develop the resist, then etch or dope through the openings.[R8]
  • Shorter light wavelengths can print finer patterns:
    • DUV (deep ultraviolet): 248 nm and 193 nm lasers.[R9]
    • EUV (extreme ultraviolet): 13.5 nm light, more than 14× shorter.[R9]
      • EUV light is made by hitting molten tin droplets (about 25 µm across) with a laser twice: once to flatten each droplet, once to turn it into a glowing plasma. This happens 50,000 times a second.[R9]
      • Air absorbs EUV, so the whole light path is in a vacuum, and it uses mirrors instead of lenses.[R10]
    • Resolution: standard EUV (numerical aperture 0.33) resolves 13 nm. High-NA EUV (NA 0.55) resolves 8 nm.[R10]
Status: High-NA EUV (as of October 2026)
  • ASML shipped the first High-NA system in December 2023.[R10]
  • By early 2026, Intel, SK hynix and Samsung had High-NA tools, and the research center imec received one on 18 March 2026.[R11][R12]
  • Reuters estimates that fewer than a dozen exist, at roughly $400 million each. That's an estimate, not an ASML list price.[R11]

What "2 nm" means, and doesn't

"3 nm", "2 nm" and "18A" are generation labels, not measurements.[R13][R14]

"I can't point to the one dimension that's 32 nm or 22 nm or 14 nm." Mark Bohr, Intel [R13]
Read the details
  • Settled: node names like "3 nm", "2 nm" and "18A" are generation labels, not measurements.[R13][R14]
    • Intel's Mark Bohr: "I can't point to the one dimension that's 32 nm or 22 nm or 14 nm."[R13]
    • By the early 2000s, the node number had "nothing to do with any dimension that you can find on the die" (Paolo Gargini, former chair of the industry roadmap).[R14]
  • Real dimensions, for scale:
    • Intel's "22 nm" FinFET had a 26 nm gate length and 8 nm-wide fins.[R14]
    • The "5 nm" node has a contacted gate pitch (spacing between gates) of 48 nm and a metal pitch of 36 nm.[R14]
    • Intel 18A (marketed as 1.8 nm-class) has a contacted gate pitch of 50 nm, more than 25× the name.[R15]
  • Industry veterans have proposed describing chips by real numbers instead: gate pitch, metal pitch, and number of stacked layers of devices.[R14]
T2

Name vs. ruler

Don't read "2 nm" as a physical size.

This demo needs JavaScript.

What this leaves outA chip has many different dimensions; only the sourced ones are shown.

D3

From transistors to gates

Two kinds of transistor, working in pairs (CMOS)

T3

Build-a-gate

See which transistors are on for each input, and why NAND/NOR are the natural 4-transistor gates.

This demo needs JavaScript.

What this leaves outReal gates have timing, power and sizing concerns; transistors are drawn as ideal switches.

Real transistor counts (standard static CMOS)

NOT2
NAND, NOR4
AND, OR6
SRAM bit6
XOR6, 8 or 12

One square = one transistor. Dashed: depends on circuit style. Sources in the table.

Read the details
GateTransistorsHow
NOT21 PMOS + 1 NMOS [R16]
NAND (2-input)42 NMOS in series, 2 PMOS in parallel [R17]
NOR (2-input)42 NMOS in parallel, 2 PMOS in series [R18]
AND (2-input)6NAND (4) + NOT (2) [R19][R20]
OR (2-input)6NOR (4) + NOT (2) [R19]
XOR (2-input)6, 8 or 12depends on circuit style [R21][R22]
SRAM memory cell (1 bit)6two cross-coupled inverters (4) + 2 access transistors [R23]
"Are transistors always grouped in 4?"

No. But the idea has two real roots:

  1. The two most basic gates, NAND and NOR, are exactly 4 transistors each.[R17][R18]
  2. The classic logic chip, the 7400 family, puts four NAND gates in one package. TI's SN74HC00 is literally named "Quadruple 2-Input NAND Gates."[R24]

Counter-examples: NOT is 2, AND/OR are 6, an SRAM cell is 6, XOR is 6–12.

D4

Every possible gate

Outputs are always exactly 0 or 1. Each gate's whole behavior fits in a small table.[R25]

ABANDORNANDNORXORXNOR
00001101
01011010
10011010
11110001
ANOT A
01
10
16possible 2-input gates: 2⁴ tables [R26]
1gate type is enough: NAND (or NOR) builds them all [R20][R25]
  1. ~1880Charles Sanders Peirce discovers it (published only in 1933).[R26]
  2. 1913Henry Sheffer publishes it, though his "stroke" meant NOR.[R26][R27]
  3. 1917Jean Nicod uses it for NAND, the meaning used today.[R27]
Read the details
  • In plain words:
    • AND: 1 only if both inputs are 1.
    • OR: 1 if either is.
    • NAND / NOR: the opposite of AND / OR.
    • XOR ("exclusive or"): 1 if the inputs differ.
    • XNOR: 1 if they're the same.
  • How many 2-input gates are possible? 16. A 2-input table has 4 rows, and each row's output can be 0 or 1, so there are 2⁴ = 16 possible tables. Logicians count the same 16 "binary connectives".[R26] Only some have common names. Others include "always 0", "always 1", "just A", and "A AND NOT B".
  • NAND can build everything. Any logic function can be made from NAND gates alone, and the same goes for NOR.[R20][R25] For example:
    • NOT A = A NAND A
    • A AND B = NOT (A NAND B)
    • A OR B = (NOT A) NAND (NOT B)
  • History:
    • Charles Sanders Peirce discovered this around 1880, but it was only published in 1933.[R26]
    • Henry Sheffer published it in 1913, though his "stroke" meant NOR.[R26][R27]
    • Jean Nicod used it for NAND in 1917, the meaning used today.[R27]
T4

Truth-table explorer

There are exactly 16 possible rules, outputs are always 0 or 1, and NAND alone can make all of them.

This demo needs JavaScript.

What this leaves outGates with more than 2 inputs. The NAND-only builds were worked out for this page and are checked against each truth table as the page runs; they are not the most efficient transistor-level designs.

D5

Gates that add and gates that remember

Adding with gates

Half adder: Sum = A XOR B, Carry = A AND B. Chain full adders and the carry "ripples" along.[R28]

Read the details
  • Half adder: adds two bits. Sum = A XOR B, Carry = A AND B.[R28]
ABCarrySum
0000
0101
1001
1110

(1 + 1 = 10 in binary: sum 0, carry 1.)

  • Full adder: adds two bits plus an incoming carry. It's two half adders plus an OR gate.[R28]
  • Ripple-carry adder: chain full adders, and each carry "ripples" to the next. It's simple, but slower than cleverer designs (carry-lookahead) used in real chips.[R28]
T5

4-bit adder

Arithmetic is just gates, and carries ripple.

This demo needs JavaScript.

What this leaves outReal CPUs use faster adder designs (carry-lookahead); no timing delays are shown.

Remembering with gates

T6

SR latch

Feedback lets gates remember one bit.

This demo needs JavaScript.

What this leaves outReal memory uses SRAM/DRAM cells and clocked flip-flops; no timing is shown.
SRAM

6 transistors per bit, holds its value while powered, fast but takes more chip area.[R23]

DRAM

1 transistor + 1 tiny capacitor per bit. The charge slowly leaks, so it must be refreshed constantly. It's denser and cheaper per bit.[R31]

D6

Bits and bytes

A byte is 8 bits, so it holds 2⁸ = 256 values (0–255). The playground below shows how.[R33]

  1. 1948"Bit" first in print, in Shannon's paper, credited to John Tukey.[R30]
  2. 1956"Byte" coined by Werner Buchholz at IBM, from "bite". 8-bit bytes adopted for Stretch.[R32]
  3. 1963ASCII: 7-bit code, 128 characters. "A" = 65.[R51]
  4. mid-1960sIBM System/360 spreads the 8-bit byte "far and wide".[R32]
  5. Sep 2026Unicode 18.0: 172,808 characters; its first 128 match ASCII.[R52][R41]
Read the details
  • Bit = binary digit, one 0 or 1. The word first appeared in print in Claude Shannon's 1948 paper, which credits it to John Tukey: "binary digits, or more briefly bits, a word suggested by J. W. Tukey."[R30]
  • Byte: coined by Werner Buchholz at IBM in 1956 while designing the Stretch computer. It was "coined from 'bite', but respelled to avoid accidental mutation to 'bit'."[R32]
    • Early bytes ranged from 1 to 6 bits. 8-bit bytes were adopted for Stretch later in 1956.[R32]
    • IBM's System/360 spread the 8-bit byte "far and wide in the mid-1960s."[R32] Bytes from 1 to 48 bits have been used; "octet" means exactly 8.[R33]
  • One byte holds 2⁸ = 256 values (0–255).[R33]
  • How bits become numbers (place value): each position is worth double the one to its right: 128, 64, 32, 16, 8, 4, 2, 1. Add up the positions holding a 1.[R34]
    • Example: 0100 0001 = 64 + 1 = 65.
  • Hexadecimal (base 16, digits 0–9 and A–F) is shorthand: one hex digit = 4 bits, so a byte is two hex digits, 00 to FF.[R35] 65 = 0x41.
T7

Byte playground

A byte is 8 switches, and the same bits can be read as a number or a letter.

This demo needs JavaScript.

What this leaves outCharacters beyond 127 use multi-byte encodings (UTF-8), so for those the demo shows a note instead of a character.

D7

From keypress to pixel

Follow the capital letter A, typed with Shift.

T8

Keypress-to-pixel pipeline

A letter on screen is a chain of codes and transistors from finger to light.

This demo needs JavaScript. All 12 steps are listed below.

What this leaves outThis shows a USB keyboard on Windows; other systems differ in details. Real steps overlap and take microseconds to milliseconds; no timings are shown, since none are sourced.
All 12 steps as text
  1. Key switch → circuit. Keys sit on a grid of row and column wires. Pressing a key connects one row to one column.[R36]
  2. The keyboard scans. Its tiny processor energizes the columns one at a time and reads all the rows, many times a second, to see which junctions are connected. Diodes stop false "ghost" presses.[R36]
  3. The keyboard sends a code, not a letter. It reports which key is down, not what character it means.[R37]
  4. Over USB: a standard keyboard report is 8 bytes: one for modifier keys (Shift, Ctrl…), one reserved, and up to six key codes.[R38] The "A" key is usage 0x04, and Left Shift is 0xE1.[R39]
  5. The OS applies your keyboard layout. The operating system turns the key code into a character, taking Shift and Caps Lock into account. The layout decides which character each key produces.[R40]
  6. The character code: "A" is Unicode U+0041, "LATIN CAPITAL LETTER A".[R41] That's decimal 65, binary 0100 0001. In UTF-8 (the web's standard encoding), it's stored as that single byte.[R42]
  7. The app receives the character and inserts it into the text. (On Windows, as a WM_CHAR message.)[R40]
  8. Font lookup: the font's character map (cmap table) maps the code to a glyph, the font's drawing of "A".[R43] Glyphs are outlines made of curves (quadratic Bézier curves in TrueType fonts).[R44]
  9. Rasterize: the outline is converted to pixels, lighting the pixels whose centers fall inside the shape. Anti-aliasing uses in-between shades on the edges so the letter looks smooth.[R45][R46]
  10. Framebuffer: the finished image of the whole screen sits in memory as a grid of pixel values.[R47]
  11. Refresh: the display redraws from that image many times a second, commonly 60 or 120 times per second (Hz).[R48]
  12. Light: each pixel is made of red, green and blue subpixels. In an LCD, a backlight shines through, and one thin-film transistor per pixel controls how much light gets through.[R49] In an OLED, each pixel makes its own light, controlled by at least two thin-film transistors, and black pixels switch fully off.[R50] So the last step is transistors too.
Background: ASCII and Unicode
  • ASCII was first published in 1963. It was a 7-bit code with 128 characters (33 control, 95 printable). It was revised in 1967.[R51]
  • Unicode extends this to every writing system. Version 18.0, released 16 September 2026, has 172,808 characters.[R52] Unicode's first 128 codes match ASCII, which is why "A" is 65 in both.[R41][R42]

D8

How long has this been going on?

T9

Timeline of switches

Feel the scale of growth, from thousands of switches to trillions in 85 years.

This demo needs JavaScript. The same data is in the table below.

What this leaves outRelays and tubes aren't directly comparable to transistors, and chips of different types (CPU, GPU, wafer-scale) are mixed.
The timeline as a table
WhenMilestoneSwitches
1941Zuse Z32,300 relays (electromagnetic switches) [R53]
1944Harvard Mark I3,500 relays [R53]
1945–46ENIACmore than 17,000 vacuum tubes [R54]
Dec 1947First transistor (point-contact, germanium), Bardeen and Brattain, Bell Labs1 [R55]
1954First silicon transistors[R96]
1958First integrated circuit (Kilby, TI)[R56]
1959Practical silicon integrated circuit, patent filed (Noyce, Fairchild)[R57]
1959–60MOSFET (Atalla and Kahng, Bell Labs)[R58]
1971Intel 4004, first microprocessor (built for a Busicom calculator)2,300 transistors [R60]
1978Intel 808629,000 [R61]
1982Intel 80286134,000 [R61]
1985Intel 80386275,000 [R61]
1989Intel 486, first x86 chip over 1 million1.2 million [R61]
1993Intel Pentium3.1 million [R61]
2006Intel Itanium 2 "Montecito"1.72 billion [R62]
2022NVIDIA H10080 billion [R66]
2024NVIDIA Blackwell (two dies)208 billion [R63]
2024Cerebras WSE-3 (a whole wafer as one chip)4 trillion [R65]
2026NVIDIA Rubin GPU (announced Jan 2026, two dies)336 billion [R64]
Status (as of October 2026) Transistor counts above are the latest published figures found. Apple's newest chips (M6, Aug 2026) don't have published counts.[R95]

D9

Is my microwave different?

Mostly the same logic, just far fewer transistors

Microcontrollers

A whole small computer on one chip. TI's 4-bit TMS1000 (1974, about $2 in volume) went into toys like the Speak & Spell. Microcontrollers now control microwave ovens and are found in large numbers in appliances and cars.[R67]

8-bit microcontrollers

Run washing machines, thermostats, smoke detectors and toasters.[R68]

Cars

Many modern cars have upwards of 100 electronic control units.[R70]

Apollo Guidance Computer

Built in the 1960s from thousands of simple chips, each holding 3-input NOR gates.[R72][R73] A real-world "build everything from one gate" machine.

Genuinely different

Mechanical thermostat

A bimetallic strip (two metals that expand at different rates) curls as the temperature changes and physically touches a contact to switch the furnace on. The strip is both the sensor and the switch. There are no transistors and no logic.[R69]

Analog electronics

Signals vary continuously (like a dimmer) instead of jumping between two values. Two-state (digital) operation is "far more reliable" than many-valued analog operation.[R71]

D10

Quantum computing: a different kind of bit

What a qubit is

Interference: the engine

T10

Interference demo

Amplitudes can cancel, and that cancellation, not "trying everything", is what quantum algorithms exploit.

This demo needs JavaScript.

What this leaves outThis is one qubit (no entanglement), and ordinary light waves interfere the same way, so it shows the amplitude rule, not where speedup comes from. Real amplitudes are complex numbers (phases). The photon is never split: it's always detected whole, at one place.[R93]

Entanglement

Myth: "A quantum computer tries every answer at once."
  • False. "Quantum computers won't solve hard problems instantly by just trying all solutions in parallel" (Scott Aaronson, quantum computing researcher).[R79]
  • He calls the "both 0 and 1 at the same time" framing "the fundamental misstep of quantum computing popularization."[R75]
  • The power comes from interference, and it only works for problems with the right mathematical structure.

What it's good for, and not

Where things stand (as of October 2026)

Tap a tile for the details.

Qubit counts~100high-quality qubits in the best machinesdetails
  • Big counts mislead: Caltech held 6,100 atom qubits in an array in 2025, but they weren't entangled or computing.[R84]
  • The best machines run on roughly 100 high-quality physical qubits.
Error correctionWorksbut only at small scaledetails
  • Many error-prone physical qubits are grouped into one more reliable logical qubit. This only helps if errors are below a threshold.[R82]
  • Google's Willow chip (Dec 2024) was the first to show errors shrinking as the code grew.[R83][R82]
  • Harvard/MIT/QuEra (Nov 2025) demonstrated a fault-tolerant architecture with up to 448 atoms.[R94]
  • Quantinuum reported a record logical fidelity in Oct 2026 (company claim).[R89]
"Quantum advantage"Contestednarrow claims, no useful advantage yetdetails
  • Google's "Quantum Echoes" (Oct 2025, peer-reviewed) claimed ~13,000× over classical.[R85]
  • IBM and UChicago claimed advantage on 70 logical qubits (Jul 2026).[R86] A classical team reproduced that result in about 37 minutes on 256 GPUs weeks later.[R87]
  • There's no consensus yet on a useful quantum advantage.
Roadmaps2029target dates: plans, not resultsdetails
  • IBM's "Starling": 200 logical qubits by 2029.[R88]
  • Quantinuum: a fault-tolerant machine "by 2029".[R89]
Real impact today: encryptionRSA out by 2035NIST's plan: deprecated after 2030, disallowed after 2035details
  • NIST finalized the first post-quantum encryption standards in August 2024.[R90]
  • Its October 2026 transition plan deprecates RSA and similar schemes after 2030 and disallows them after 2035.[R91]
  • Estimates suggest breaking RSA-2048 would take under 1 million noisy qubits running for under a week (Gidney 2025, an estimate).[R92] That is far beyond today's machines.

D11

Self-check

Progress is saved on this device only.

T11

Match and quiz

Lock in the key numbers and ideas.

This demo needs JavaScript.

D12

Back to the model

On the ladder

The transistor is the computer side of stage 3, "smallest switch", paired with the ion channel. Gates and AI "neurons" sit at stage 5, where the analogy with a real neuron is weak.

← Back to the matter-to-thought ladder

What this page simplifies

  1. Transistors as ideal switches. Real ones turn on gradually and leak slightly when off.
  2. The T1 cross-section is a 2D sketch. Modern transistors are 3D fins or nanosheets.
  3. Gate transistor counts are for standard static CMOS. Other circuit styles use different counts (e.g., XOR can be 6, 8 or 12).[R21]
  4. AND = 6 and OR = 6 are sums of sourced parts (a NAND or NOR plus an inverter), the standard construction.[R19][R20]
  5. The keypress chain shows a USB keyboard on Windows. Other operating systems differ in details.
  6. Ripple-carry is the teaching adder. Real processors use faster designs.[R28]
  7. The interference demo (T10) is one qubit. It shows the amplitude rule, not entanglement or the source of quantum speedup. Real amplitudes are complex numbers.
  8. Status boxes are snapshots dated October 2026. Transistor counts, High-NA EUV and quantum status change fast.
  9. Estimates are labeled: the ~$400M High-NA price, "fewer than a dozen" High-NA tools, the RSA-2048 qubit estimate, and 100+ car ECUs are estimates or approximate figures.
  10. Wikipedia is a secondary source for some logic facts (XOR counts, flip-flops, framebuffer, refresh rates, display types). These are marked (WP) in the reference list.

Sources

Sources marked (WP) are Wikipedia, used as secondary sources where no better source was found. "Read Oct 2026" marks pages whose content may change.

Transistor physics and fabrication

  1. R1HyperPhysics (Georgia State University). Doping. hyperphysics.gsu.edu
  2. R2Ye, Ernst & Khare (2019). The Nanosheet Transistor Is the Next (and Maybe Last) Step in Moore's Law. IEEE Spectrum, 30 Jul 2019. spectrum.ieee.org
  3. R3Intel (2011). Intel Reinvents Transistors Using New 3-D Structure. 4 May 2011. intc.com
  4. R4Moore, S. K. (2024). TSMC Lifts the Curtain on Nanosheet Transistors. IEEE Spectrum, 12 Dec 2024. spectrum.ieee.org
  5. R5TSMC. 2nm Technology (read Oct 2026). tsmc.com
  6. R6Intel Foundry. Intel 18A (read Oct 2026). intel.com
  7. R7ASML. 6 crucial steps in semiconductor manufacturing (updated 4 Oct 2023). asml.com
  8. R8Computer History Museum. 1955: Photolithography Techniques Are Used to Make Silicon Devices. computerhistory.org
  9. R9ASML. Light and lasers. asml.com
  10. R10ASML. EUV lithography systems (read Oct 2026). asml.com
  11. R11TrendForce (2026). imec Secures ASML's Most Advanced EXE:5200 High-NA EUV… 19 Mar 2026 (cites Reuters for the unit count and price estimate). trendforce.com
  12. R12imec (2026). Imec receives the world's most advanced High NA EUV system. 18 Mar 2026. imec-int.com
  13. R13Courtland, R. (2013). The Status of Moore's Law: It's Complicated. IEEE Spectrum, 28 Oct 2013. spectrum.ieee.org
  14. R14Moore, S. K. (2020). A Better Way to Measure Progress in Semiconductors. IEEE Spectrum, 21 Jul 2020. spectrum.ieee.org
  15. R15Intel (2026). Intel Foundry Details Process Milestones, Future Innovation at VLSI Symposium. 16 Jun 2026. intel.com
  16. R97Samsung Global Newsroom (2022). Samsung Begins Chip Production Using 3nm Process Technology With GAA Architecture. 30 Jun 2022. news.samsung.com

Logic gates and circuits

  1. R16UP Microelectronics Lab. CoE 197U: CMOS Gates. classes.up-microlab.org
  2. R17Univ. Hamburg TAMS (Hades). CMOS NAND2 gate. tams.informatik.uni-hamburg.de
  3. R18Univ. Hamburg TAMS (Hades). CMOS NOR2 gate. tams.informatik.uni-hamburg.de
  4. R19Univ. Hamburg TAMS (Hades). AND gate (andbig). tams.informatik.uni-hamburg.de
  5. R20MIT OCW. 6.004 Computation Structures (Spring 2017), lecture transcript. ocw.mit.edu
  6. R21(WP) XOR gate. en.wikipedia.org
  7. R22Univ. Hamburg TAMS (Hades). CMOS XOR with transmission gate. tams.informatik.uni-hamburg.de
  8. R23(WP) Static random-access memory. en.wikipedia.org
  9. R24Texas Instruments. SN74HC00: Quadruple 2-Input NAND Gates. ti.com
  10. R25(WP) Logic gate. en.wikipedia.org
  11. R26Internet Encyclopedia of Philosophy. The Sheffer Stroke. iep.utm.edu
  12. R27(WP) Sheffer stroke. en.wikipedia.org
  13. R28(WP) Adder (electronics). en.wikipedia.org
  14. R29(WP) Flip-flop (electronics). en.wikipedia.org
  15. R30Shannon, C. E. (1948). A Mathematical Theory of Communication. Bell System Technical Journal 27. people.math.harvard.edu (PDF)
  16. R31(WP) Dynamic random-access memory. en.wikipedia.org

Bits, bytes, encoding and display

  1. R32Buchholz, W. (1977). Origin of the word "byte". BYTE, Feb 1977, p.144 (Computer History Museum archive). archive.computerhistory.org (PDF)
  2. R33(WP) Byte. en.wikipedia.org
  3. R34(WP) Binary number. en.wikipedia.org
  4. R35(WP) Hexadecimal. en.wikipedia.org
  5. R36QMK Firmware. How a Keyboard Matrix Works. docs.qmk.fm
  6. R37QMK Firmware. How Keyboards Work. docs.qmk.fm
  7. R38USB-IF. Device Class Definition for HID, v1.11 (Appendix B, boot keyboard report). usb.org (PDF)
  8. R39USB-IF. HID Usage Tables v1.7 (27 Jan 2026), page 0x07: 0x04 = Keyboard A, 0xE1 = Left Shift. usb.org (PDF)
  9. R40Microsoft Learn. Keyboard Input Overview. learn.microsoft.com
  10. R41Unicode Consortium. Unicode Character Database 18.0.0, UnicodeData.txt. unicode.org
  11. R42IETF (2003). RFC 3629: UTF-8, a transformation format of ISO 10646. rfc-editor.org
  12. R43Microsoft Learn. OpenType spec: cmap table. learn.microsoft.com
  13. R44Apple. TrueType Reference Manual, Ch. 1: Digitizing Letterform Designs. developer.apple.com
  14. R45FreeType. API Reference: Glyph Retrieval (FT_Render_Mode). freetype.org
  15. R46FreeType. Glyph Conventions, section 6. freetype.org
  16. R47(WP) Framebuffer. en.wikipedia.org
  17. R48(WP) Refresh rate. en.wikipedia.org
  18. R49(WP) Thin-film-transistor liquid-crystal display. en.wikipedia.org
  19. R50(WP) AMOLED. en.wikipedia.org
  20. R51IEEE / ETHW. Milestones: American Standard Code for Information Interchange (ASCII), 1963. ethw.org
  21. R52Unicode Consortium (2026). Announcing the Unicode Standard, Version 18.0. 16 Sep 2026. blog.unicode.org

History and chips

  1. R53Computer History Museum. Timeline of Computer History: Computers. computerhistory.org
  2. R54Penn Almanac (2026). Penn's ENIAC, the world's first electronic computer, turns 80. 3 Mar 2026. almanac.upenn.edu
  3. R55Computer History Museum. 1947: Invention of the Point-Contact Transistor. computerhistory.org
  4. R56Computer History Museum. 1958: All Semiconductor "Solid Circuit" is Demonstrated. computerhistory.org
  5. R57Computer History Museum. 1959: Practical Monolithic Integrated Circuit Concept Patented. computerhistory.org
  6. R58Computer History Museum. 1960: Metal Oxide Semiconductor (MOS) Transistor Demonstrated. computerhistory.org
  7. R59Computer History Museum. 1965: "Moore's Law" Predicts the Future of Integrated Circuits. computerhistory.org
  8. R60Computer History Museum. 1971: Microprocessor Integrates CPU Function onto a Single Chip. computerhistory.org
  9. R61Computer History Museum. Intel "x86" Family and the Microprocessor Wars. computerhistory.org (note: CHM dates the 8086 to 1976, the start of design; it was released in 1978)
  10. R62CIO (2006). Intel to launch Montecito server chip Tuesday. 14 Jul 2006. cio.com
  11. R63NVIDIA. NVIDIA Blackwell Architecture (read Oct 2026). nvidia.com
  12. R64NVIDIA Developer Blog (2026). Inside the NVIDIA Rubin Platform: Six New Chips, One AI Supercomputer. 5 Jan 2026. developer.nvidia.com
  13. R65Cerebras (2024). Cerebras Announces Third Generation Wafer Scale Engine. 13 Mar 2024. cerebras.ai
  14. R66NVIDIA Developer Blog (2022). NVIDIA Hopper Architecture In-Depth. 22 Mar 2022. developer.nvidia.com
  15. R95Apple Newsroom (2026). Apple introduces M6 and M5 Ultra… 25 Aug 2026. apple.com
  16. R96Computer History Museum. 1954: Silicon Transistors Offer Superior Operating Characteristics. computerhistory.org

Simpler devices

  1. R67Computer History Museum. 1974: General-Purpose Microcontroller Family is Announced. computerhistory.org
  2. R68DigiKey (2011). Application Ideas for 8-bit Low-Pin-Count Microcontrollers. 8 Aug 2011. digikey.co.nz
  3. R69UCSB Physics Lecture Demonstrations. Bimetallic strip. web.physics.ucsb.edu
  4. R70Venkat, S. (2021). Automotive Functional Safety Compliance In EDA Tools And IP. Semiconductor Engineering, 1 Feb 2021. semiengineering.com
  5. R71IIT (ISM) Dhanbad. Electronics Class Notes: Analog and Digital Signals. people.iitism.ac.in
  6. R72Computer History Museum. 1962: Aerospace Systems Are the First Applications for ICs in Computers. computerhistory.org
  7. R73Leibson, S. (2024). The First ICs on the Moon: The Apollo Guidance Computer, Part 1. EE Journal, 10 Jun 2024. eejournal.com

Quantum computing

  1. R74IBM Think. What is quantum computing? (10 Jun 2025, updated 2 Apr 2026). ibm.com
  2. R75Aaronson, S. (2021). What Makes Quantum Computing So Hard to Explain? Quanta Magazine, 8 Jun 2021. quantamagazine.org
  3. R76Y Combinator (2018). Scott Aaronson on Computational Complexity Theory and Quantum Computers. 29 Jun 2018. ycombinator.com
  4. R77Caltech Science Exchange. What Is Quantum Entanglement? scienceexchange.caltech.edu
  5. R78Shalm, K. (2025). Quantum and Dance: It Takes 2 to Entangle. NIST Taking Measure, 14 Apr 2025. nist.gov
  6. R79Aaronson, S. Shtetl-Optimized (blog masthead, read 31 Oct 2026). scottaaronson.blog
  7. R81(WP) Grover's algorithm. en.wikipedia.org
  8. R82Brubaker, B. (2024). Quantum Computers Cross Critical Error Threshold. Quanta Magazine, 9 Dec 2024. quantamagazine.org
  9. R83Google (2024). Meet Willow, our state-of-the-art quantum chip. 9 Dec 2024. blog.google
  10. R84Caltech (2025). Caltech Team Sets Record with 6,100-Qubit Array. 24 Sep 2025. caltech.edu
  11. R85Google (2025). Our Quantum Echoes algorithm… 22 Oct 2025. blog.google
  12. R86IBM Newsroom (2026). IBM and The University of Chicago Demonstrate Quantum Advantage… 30 Jul 2026. newsroom.ibm.com
  13. R87Quantum Timeline. IBM and partners claim quantum advantage with built-in accuracy checks (covers the Aug 2026 classical reproduction). quantumtimeline.org
  14. R88IBM Quantum (2025). IBM lays out clear path to fault-tolerant quantum computing. 10 Jun 2025. ibm.com
  15. R89Quantinuum (2026). Quantinuum Breaks Error-Correction World Record by 10x… 19 Oct 2026 (company press release). quantinuum.com
  16. R90NIST (2024). NIST Releases First 3 Finalized Post-Quantum Encryption Standards. 13 Aug 2024. nist.gov
  17. R91Quantum Computing Report (2026). NIST releases final IR 8547… 27 Oct 2026 (summary of NIST IR 8547; primary document). quantumcomputingreport.com
  18. R92Gidney, C. (2025). How to factor 2048 bit RSA integers with less than a million noisy qubits. arXiv:2505.15917, 21 May 2025. arxiv.org
  19. R93Rioux, F. Single-photon Interference: Third Version. Chemistry LibreTexts. chem.libretexts.org
  20. R94Quantum Computing Report (2025). Harvard and collaborators demonstrate scalable fault-tolerant architecture with 448 neutral atom qubits. 23 Nov 2025. quantumcomputingreport.com

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